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GENLINXTM GS9015A
Serial Digital Reclocker
DATA SHEET
FEATURES * * * reclocking of SMPTE 259M signals operational to 400 Mb/s adjustment free reclocker when used with the GS9000B or GS9000S decoder and GS9010A Automatic Tuning Sub-system 28 pin PLCC packaging DEVICE DESCRIPTION The GS9015A is a monolithic IC designed to receive SMPTE 259M serial digital video signals. This device performs the function of data and clock recovery. It interfaces directly with the GENLINX TM GS9000B or GS9000S Decoder. While there are no plans to discontinue the GS9015A, Gennum has developed a successor product with improved features and performance called the GS9035. The GS9035 is recommended for new designs. The VCO centre frequencies are controlled by external resistors which can be selected by applying a two bit binary code to the Standards Select input pins. Alternatively, the GS9015A can be used with the GS9010A to form an adjustment free reclocker system. The GS9015A is packaged in a 28 pin PLCC operating from a single +5 or -5 volt supply. SPECIAL NOTE: RVCO1 and RVCO2 are functional over a reduced temperature range of TA=0C to 50C. RVCO0 and RVCO3 are functional over the full temperature range of TA=0C to 70C. This limitation does not affect operation with the GS9010A ATS.
*
APPLICATIONS * 4SC, 4:2:2 and 360 Mb/s serial digital interfaces ORDERING INFORMATION
PART NUMBER GS9015ACPJ GS9015ACTJ PACKAGE 28 Pin PLCC 28 Pin PLCC Tape TEMPERATURE 0O C to 70O C 0O C to 70O C
GS9015A
24 DIGITAL 5,6 IN DATA LATCH 25 22 23 SERIAL DATA SERIAL DATA SERIAL CLOCK SERIAL CLOCK
PHASE
COMPARATOR
CARRIER 19 DETECT
10 CARRIER DETECT CHARGE PUMP 20 /2
/2
LOOP FILTER 12 PLL
VCO
STANDARD SELECT
SS0 SS1
21
13 14 15 17
FUNCTIONAL BLOCK DIAGRAM
Revision Date: April 1998 Document No. 520 - 99 - 05
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 Web Site: www.gennum.com E-mail: info@gennum.com
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage Input Voltage Range (any input) DC Input Current (any one input) Power Dissipation Operating Temperature Range Storage Temperature Range Lead Temperature (soldering, 10 seconds) VALUE/UNITS 5.5 V VCC+0.5 to VEE-0.5 V 5 mA 750 mW 0C TA 70C -65C TS150C 260C CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION
GS9015A RECLOCKER DC ELECTRICAL CHARACTERISTICS
V S = 5V, TA = 0C to 70C, R L = 100 to (VCC - 2V) unless otherwise shown.
PARAMETER Supply Voltage Power Consumption Supply Current (Total) Serial Data & Clock Output Logic Inputs (1, 10, 20, 21) Carrier Detect Output Voltage - High - Low - High - Low
SYMBOL VS PD IS V OH V OL V IH MIN V IL MAX V CDL V CDH
CONDITIONS Operating Range
MIN 4.75 -
TYP 5.0 330 87 0.2
MAX 5.25 500 120 -0.88 -1.6 +0.8 0.4 -
UNITS V mW mA V V V V V V
NOTES
see Figure11 with respect to V CC with respect to VCC with respect to V EE with respect to V EE
with respect to VEE Open Collector - Active High
T A = 25C T A = 25C
-1.025 -1.9 +2.0 -
RL = 10 k to VCC 4.0
5.0
GS9015A RECLOCKER AC ELECTRICAL CHARACTERISTICS
V S = 5V, TA = 0C to 70C, R L = 100 to (VCC - 2V) unless otherwise shown.
PARAMETER Serial Data Bit Rate Serial Clock Frequency Output Signal Swing Serial Data to Serial Clock Synchronization Lock Times Jitter Direct Digital Input Levels (5, 6)
SYMBOL BR SDO SLK VO td
CONDITION T A = 25C T A = 25C T A = 25C See Waveforms
MIN 100 100 700 -
TYP 800 -500
MAX 400 400 900 -
UNITS Mb/s MHz mV p-p ps
NOTES
see Figure 9 see Figure10 Data lags Clock
t LOCK tJ V DDI
see note 1 T A= 25C, 270 Mb/s
200
100 -
10 2000
s ps p-p mVp-p see Figure12 Differential Drive
NOTES: 1. Switching between two sources of the same data rate.
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2
tD
tD
SERIAL DATA OUT (SD0)
SERIAL CLOCK OUT (SCK)
50%
50%
Fig.1 Waveforms
GS9015A Reclocking Receiver - Detailed Device Description The GS9015A Reclocking Receiver is a bipolar integrated circuit containing circuitry necessary to re-clock and regenerate the NRZI serial data stream. Packaged in a 28 pin PLCC, the receiver operates from a single five volt supply at data rates to 400 Mb/s. Typical power consumption is 330 mW. Typical output jitter is 100 ps at 270 Mb/s. Serial Digital signals are applied to digital inputs DDI and DDI (pins 5,6). Phase Locked Loop The phase comparator itself compares the position of transitions in the incoming signal with the phase of the local oscillator (VCO). The error-correcting output signals are fed to the charge pump in the form of short pulses. The charge pump converts these pulses into a "charge packet" which is accurately proportional to the system phase error. The charge packet is then integrated by the second-order loop filter to produce a control voltage for the VCO. During periods when there are no transitions in the signal, the loop filter voltage is required to hold precisely at its last value so that the VCO does not drift significantly between corrections. Commutating diodes in the charge pump keep the output leakage current extremely low, minimizing VCO frequency drift. The VCO is implemented using a current-controlled multivibrator, designed to deliver good stability, low phase noise and wide operating frequency capability. The frequency range is design-limited to 10% about the oscillator centre frequency. VCO Centre Frequency Selection The centre frequency of the VCO is set by one of four external current reference resistors (RVCO0-RVCO3) connected to pins 13,14,15 or 17. These are selected by two logic inputs SS0 and SS1 (pins 20, 21) through a 2:4 decoder according to the following truth table.
SS1 0 0 1 1
SS0 0 1 0 1
Resistor Selected RVCO0 (13) RVCO1 (14) RVCO2 (15) RVCO3 (17)
As an alternative, the GS9010A Automatic Tuning Sub-system and the GS9000B or GS9000S Decoder may be used in conjunction with the GS9015A to obtain adjustment free and automatic standard select operation (see Figure17). With the VCO operating at twice the clock frequency, a clock phase which is centred on the eye of the locked signal is used to latch the incoming data, thus maximising immunity to jitter-induced errors. The alternate phase is used to latch the output re-clocked data SDO and SDO (pins 25, 24). The true and inverse clock signals themselves are available from the SCO and SCO pins 23 and 22.
3
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VEE1
VEE1
VEE1 VEE1 VEE1 VEE2 VCC3
4 DDI DDI VCC1 VEE1 VEE1 /2 EN VEE3 5 6 7 8 9 10 11 12
3
2
28
27
26 25 24 23 SD0 SD0 SC0 SC0 SS1 SS0 CD
GS9015A TOP VIEW
22 21 20 19
13
14
15
16
17
18
LOOP RVCO0 RVCO1 RVCO2 VEE3 FILT
RVCO3 VCC2
Fig. 2 GS9015A Pin Connections
GS9015A PIN DESCRIPTIONS PIN NO. 1 2 3 4 5,6 SYMBOL VEE1 VEE1 VEE1 VEE1 DDI/DDI Input TYPE DESCRIPTION Power Supply. Most negative power supply connection. Power Supply. Most negative power supply connection. Power Supply. Most negative power supply connection. Power Supply. Most negative power supply connection. Direct Data Inputs (true and inverse). Pseudo-ECL, differential serial data inputs. They may be directly driven from true ECL drivers when VEE = -5V and VCC = 0 V. 7 8, 9 10 11 12 13 VCC1 VEE1 /2 EN VEE3 LOOP FILT RVCO0 Input Input Power Supply. Most positive power supply connection. (Phase Detector, Carrier Detect). Power Supply. Most negative power supply connection. /2 Enable-TTL compatible input used to enable the divide by 2 function. Power Supply. Most negative power supply connection. (VCO, MUX, Standard Select) Loop Filter. Node for connecting the loop filter components. VCO Resistor 0. Analog current input used to set the centre frequency of the VCO when the two Standard Select bits (pins 20 and 21) are set LOW. A resistor is connected from this pin to VEE. 14 RVCO1 Input VCO Resistor 1. Analog current input used to set the centre frequency of the VCO when Standard Select bit 0 (pin 20) is set HIGH and bit 1 (pin 21) is set LOW. A resistor is connected from this pin to VEE. 15 RVCO2 Input VCO Resistor 2. Analog current input used to set the centre frequency of the VCO when Standard Select bit 0 (pin 20) is set LOW and bit 1 (pin 21) is set HIGH. A resistor is connected from this pin to VEE. 16 17 VEE3 RVCO3 Input Power Supply. Most negative power supply connection. VCO Resistor 3. Analog current input used to set the centre frequency of the VCO when the two Standard Select bits (pins 20 and 21) are set HIGH. A resistor is connected from this pin to VEE.
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4
GS9015A PIN DESCRIPTIONS cont.
PIN NO 18 19
SYMBOL VCC2 CD
TYPE
DESCRIPTION Power Supply. Most positive power supply connection. (VCO, MUX, Standard Select).
Output
Carrier Detect. Open collector output which goes HIGH when a signal is present at either the Serial Data inputs or the Direct Digital inputs. This output is used in conjunction with the GS9000B or GS9000S in the Automatic Standards Select Mode to disable the 2 bit standard select counter. This pin should see a low AC impedance (e.g. 1nF to AC Gnd)
20,21
SS0, SS1 Inputs
Standard Select Inputs. TTL inputs to the 2:4 multiplexer used to select one of four VCO centre frequency setting resistors (RVCO0 - RVCO3). When both SS0 and SS1 are LOW, RVCO0 is selected. When SS0 is HIGH and SS1 is LOW, RVCO1 is selected. When SS0 is LOW and SS1 is HIGH, RVCO2 is selected and when both SS0 and SS1 are HIGH, RVCO3 is selected. These pins should see a low AC impedance (e.g. 1nF to AC Gnd)
22,23
SCO/SCO Outputs
Serial Clock Outputs (inverse and true). Pseudo-ECL differential outputs of the extracted serial clock. These outputs require a 390 pull-down resistors to V EE.
24,25
SDO/SDO Outputs
Serial Data Outputs (inverse and true). Pseudo-ECL differential outputs of the regenerated serial data. These outputs require a 390 pull-down resistors to V EE.
26 27 28
VCC3 VEE2 VEE1
Power Supply. Most positive power supply connection. (ECL Outputs). Power Supply. Most negative power supply connection. (Phase Detector, Carrier Detect) Power Supply. Most negative power supply connection.
INPUT / OUTPUT CIRCUITS
VCC + 1.2V
2k
2k
1k
1k
DDI Pin 5 DDI Pin 6 380A
+ 1.6V -
Fig. 3 Pins 1, 5 and 6
5
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INPUT / OUTPUT CIRCUITS cont.
IVCO
(1.9 - 2.4V)
LOOP FILTER (1.8 - 2.7V)
Pin 13 RVCO 0 Pin 14 RVCO 1 Pin 15 RVCO 2
400 400 400 400
Pin 17 RVCO 3
Fig. 4 Pins 13, 14, 15 and 17
VCC VCC3 200
200
10k
10k SDO or SCO Pin 25, 24 SDO or SCO Pin 23, 22 VCC
VCC 3k
800
Fig. 5 Pins 25, 24, 23 and 22
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6
INPUT / OUTPUT CIRCUITS cont.
VCC
VCC
VCC
VCC 10k
1.5k
2k
CD Pin 19
1k
LOOP FILTER Pin 12
Fig. 7 Pin 19
Fig. 6 Pin 12
VCC 40A
VCC 40A
VCC 18A
VCC
VCC
SS1 Pin 21
/2 EN Pin 10 SSO Pin 20
55A
480A
+ -
1.6V
Fig. 8 Pins 20, 21 and 10
7
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TYPICAL PERFORMANCE CURVES
(VS = 5V, TA = 25C unless otherwise shown)
500 450
900
850 400
SERIAL OUTPUTS (mV) (p-p)
VS = 5.25V 800 VS = 5.00V
FREQUENCY (MHz)
350 300 250 /2 OFF 200 /2 ON 150 100 50
750
700
VS = 4.75V
650
600 1 2 3 4 5 6 7 8 9 10 0 10 20 30 40 50 60 70
FREQUENCY SETTING RESISTANCE (k)
TEMPERATURE (C)
Fig. 9 Clock Frequency
Fig. 10 Serial Outputs
105 100 V S = 5.25V 95 90 85 VS = 4.75V 80 75 70 65 0 10 20 30 40 50 60 70
400 350 300
CURRENT (mA)
JITTER p-p (ps)
V S = 5.00V
250 /2 OFF 200 150 100 /2 ON 50 0 100 150 200 250 300 350 400
TEMPERATURE (C)
Fig. 11 Supply Current
DATA RATE (Mb/s)
Fig. 12 Output Jitter
520 - 99 - 05
8
+5V
0.1
390 4
VEE1 VEE1
3
VEE1
2
VEE1
1 28 27 26
VEE1 VEE2 VCC3
390 25 24 23 22 100 100 100 100 390 390 CARRIER DETECT OUTPUT 10k +5V 0.1 DATA DATA CLOCK CLOCK
+5V
ECL DATA INPUTS
0.1
5 DDI 6 DDI 7 VCC1 8 VEE1 9 VEE1 10 /2 11 VEE3
SDO SDO SCO
GS9015A
SCO
+5V SS1 21 SS0 20
RVCO0 RVCO1 RVCO2 RVCO3 LOOP VCC2
CD
19
12 13 14 15 16 17 18
5.6p +5V 10n /2 /1
910
VEE3
See Figure 15
STAR ROUTED
LOOP VOLTAGE TEST POINT
All resistors in ohms, all capacitors in microfarads unless otherwise stated.
Fig. 13 GS9015A Typical Test Circuit Using +5V Supply
TEST SETUP Figure 13 shows a typical circuit for the GS9015A using a +5 volt supply. Figure 14 shows the GS9015A connections when using a -5 volt supply. The 0.1F decoupling capacitors must be placed as close as possible to the corresponding VCC pins. The layout of the loop filter and RVCO components requires careful attention. This has been detailed in an application note entitled "Optimizing Circuit and Layout Design of the GS9005A/15A", Document No. 521 - 32 - 00. The loop voltage can be conveniently measured across the 10 nF capacitor in the loop filter. Tuning procedures are described in the Temperature Compensation Section (page 11). The fixed value frequency setting resistors should be placed close to the corresponding pins on the GS9015A. The Carrier Detect is an open-collector active high output requiring a pull-up resistor of approximately 10 k. The SS0, SS1, and CD pins should see a low AC impedance. This is particularly important when driving the SS0, SS1 pins with external logic. The use of 1nF decoupling capacitors at these pins ensures this.
9
520 - 99 - 05
0.1 -5V 390 4
VEE1 VEE1
3
VEE1
2
VEE1
1 28 27 26
VEE1 VEE2 VCC3
390 25 24 23 22 21 20 19 100 100 100 100 390 390
-5V DATA DATA CLOCK CLOCK
ECL DATA INPUTS 0.1
5 6 7
DDI DDI
SDO SDO SCO
VCC1 8 VEE1 9 VEE1 10 /2
LOOP
GS9015A
SCO SS1 SS0
RVCO0
RVCO1
RVCO2
RVCO3
V EE3
11 VEE3 -5V
VCC2
CD 10k
CARRIER DETECT OUTPUT
12 13 14 15 16 17 18
0.1 5.6p 10n 910 -5V
/2 /1 See Figure 15 STAR ROUTED -5V -5V LOOP VOLTAGE -5V
All resistors in ohms, all capacitors in microfarads unless otherwise stated.
Fig. 14 GS9015A Typical Test Circuit Using -5V Supply
VCO Frequency Setting Resistors There are two modes of VCO operation available in the GS9015A depending on the state of the / 2 block. The / 2 block is enabled according to : / 2 ENABLE = /2 * SS1. When the /2 ENABLE (pin 10) is LOW, any of the four VCO frequency setting resistors, RVCO0 through RVCO3, (pins 13, 14, 15 and 17) may be used for any data r a t e f r o m 100 Mb/s t o 4 0 0 M b / s . F o r e x a m p l e , f o r 143 Mb/s data rate, the value of the total RVCO resistance is approximately 6k8 and f o r 2 7 0 M b / s o p e r a t i o n , t h e v a l u e i s approximately 3k5. The 5k potentiometers will then tune the desired data rate near their mid-points. Jitter performance at the lower data rates (143, 177 Mb/s) is improved by operating the VCO at twice the normal frequency. This is accomplished by enabling the divide by two block in the PLL section of the GS9015A. When /2 (Pin 10) is HIGH, two of the RVCO pins are assigned to data rates below 200 Mb/s and two are assigned to data rates over 200 Mb/s. The selection is dependent upon the level of STANDARD SELECT BIT, SS1 (pin 21). When SS1 is LOW, RVCO0 and RVCO1 (pins 13 and 14) are used for the higher data rates. When SS1 is HIGH, the VCO frequency is now twice the bit rate and its frequency is set by RVCO2 and RVCO3 (pins 15 and 17). For 143 Mb/s and 270 Mb/s operation, (the VCO is at 286 MHz and 270 MHz respectively) the total resistance required is approximately the same for both data rates. This also applies for 177 Mb/s and 360 Mb/s operation (the VCO is tuned to 354 MHz and 360 MHz respectively). This means that one potentiometer may be used for each frequency pair with only a small variation of the fixed resistor value. This halves the number of adjustments required.
520 - 99 - 05
10
Temperature Compensation Figure 15 shows the connections for the frequency setting resistors for the various data rates. The compensation shown for 360 Mb/s and 177 Mb/s with Divide by 2 ON, is useful to a maximum ambient temperature of 50C. If the Divide by 2 function is not enabled by the /2 ENABLE input, no compensation is needed for the 143 Mb/s and 177 Mb/s data rates. The resistor connections are shown in Figure 16. In both cases , the 0.1F capacitor that bypasses the potentiometer should be star routed to VEE3.
1k
5k 0.1F
VEE Divide by 2 is OFF 143Mb/s and 177 Mb/s using any R VCO pins
Fig. 16
5.6k 1N914 5k 1.3k 4.3k 1N914 5k 1.3k
Non - Temperature Compensated Resistor Values for 143 Mb/s and 177 Mb/s
0.1F
0.1F
Loop Bandwidth
VEE Divide by 2 is OFF VEE Divide by 2 is ON
270 Mb/s using RVCO0 or R VCO1 143 Mb/s using RVCO2 or R VCO3
The loop bandwidth is dependant upon the internal PLL gain constants along with the loop filter components connected to pin 12. In addition, the impedance seen by the RVCO pin also influences the loop characteristics such that as the impedance drops, the loop gain increases. Applications Circuit
1k
1k
1k
0.1F
1k 0.1F 1N914 VEE Divide by 2 is ON 177 Mb/s using RVCO2 or R VCO3
Figure 17 shows an application of the GS9015A in an adjustment free, multi-standard serial to parallel convertor. This circuit uses the GS9010A Automatic Tuning Subsystem IC and a GS9000B or GS9000S Decoder IC. The GS9010A ATS eliminates the need to manually set or externally temperature compensate the Receiver or Reclocker VCO. The GS9010A can also determine whether the incoming data stream is 4sc NTSC,4sc PAL or component 4:2:2. The GS9010A includes a ramp generator/oscillator which repeatedly sweeps the Reclocker VCO frequency over a set range until the system is correctly locked. An automatic fine tuning (AFT) loop maintains the Reclocker VCO control voltage at it's centre point through continuous, long term adjustments of the VCO centre frequency. During normal operation, the GS9000B or GS9000S Decoder provides continuous HSYNC pulses which disable the ramp/oscillator of the GS9010A. This maintains the correct Reclocker VCO frequency. When an interruption to the incoming data stream is detected by the Reclocker, the Carrier Detect goes LOW and opens the AFT loop in order to maintain the correct VCO frequency for a period of at least 2 seconds. This allows the Reclocker to rapidly relock when the signal is re-established.
1N914 VEE Divide by 2 is OFF 360 Mb/s using RVCO0 or R VCO1
Fig. 15 Frequency Setting Resistor Values & Temperature Compensation
Temperature Compensation Procedure In order to correctly set the VCO frequency so that the PLL will always re-acquire lock over the full temperature range, the following procedure should be used. The circuit should be powered on for at least one minute prior to starting this procedure. Monitor the loop filter voltage at the junction of the loop filter resistor and 10 nF loop filter capacitor (LOOP FILTER TEST POINT). Using the appropriate network shown above, the VCO frequency is set by first tuning the potentiometer so that the PLL loses lock at the low end (lowest loop filter voltage). The loop filter voltage is then slowly increased by adjusting the the potentiometer to determine the error free low limit of the capture range. Error free operation is determined by using a suitable CRC or EDH measurement method to obtain a stable signal with no errors. Record the loop filter voltage at this point as VCL. Now adjust the potentiometer so that the loop filter voltage is 250 mV above VCL. 11
520 - 99 - 05
Application Note - PCB Layout Special attention must be paid to component layout when designing high performance serial digital receivers. For background information on high speed circuit and layout design concepts, refer to Document No. 521-32-00, "Optimizing Circuit and Layout Design of the GS90005A/15A". A recommended PCB layout can be found in the Gennum Application Note "EB9010B Deserializer Evaluation Board" The use of a star grounding technique is required for the loop filter components of the GS9005A/15A. Controlled impedance PCB traces should be used for the differential clock and data interconnection between the GS9005A and the GS9000B or GS9000S. These differential traces must not pass over any ground plane discontinuities. A slot antenna is formed when a microstrip trace runs across a break in the ground plane. The series resistors at the parallel data output of the GS9000B or GS9000S are used to slow down the fast rise/fall time of the GS9000B or GS9000S outputs. These resistors should be placed as close as possible to the GS9000B or GS9000S output pins to minimize radiation from these pins.
VCC +5V + 10 DVCC +5V + SWF
10
100
3.3k
DGND
100
VCC 0.1
GND
DGND
100
DGND 390
VSS
SYNC WARNING FLAG DGND 4
SWF
HSYNC OUTPUT PARALLEL DATA BIT 9 PARALLEL DATA BIT 8 100 100 100 100 100 100 100 DVCC PARALLEL DATA BIT 7 PARALLEL DATA BIT 6 PARALLEL DATA BIT 5 PARALLEL DATA BIT 4 PARALLEL DATA BIT 3 PARALLEL DATA BIT 2 PARALLEL DATA BIT 1 PARALLEL DATA BIT 0 PARALLEL CLOCK OUT
3
VSS
2
HSYNC
1
PD9
28 27 26
PD8 VSS
4
VEE1 VEE1
3
VEE1
2
VEE1
1
VEE1
28 27 26
VEE2 VCC3
390 25 24 100 100 100 100
VCC
25 24 23 22 21 20
VCC
SERIAL DIGITAL INPUT
5 6 7
DDI DDI VCC1
SDO SDO
5 6 7 8 9 10 11
SDI SDI SCI SCI SS1 SS0
PD7 (3) PD6 PD5 PD4 PD3 PD2
PCLK
0.1
GS9015A
8 VEE1 9 VEE1 10 /2
LOOP
SCO 23 SCO 22 SS1 21 SS0 20
GS9000B or GS9000S
390 390
PD1 19
PDO VDD
RVCO0
RVCO1
RVCO2
RVCO3
VDD
VDD
VEE3
VCC2
VEE3
11
5.6p
12 13 14 15 16 17 18
VCC
DVCC
12 13 14 15 16
SCE
SST
SWC
CD 19
17
18 0.1
SYNC CORRECTION ENABLE
910 10n (1)
0.1
0.1
100
100
DGND
DGND 1.2k VCC 1.2k 0.1
(2)
DVCC
50k
68k
22n
VCC 120 STAR ROUTED DGND
GS9010A
(1)
6.8 6.8
+
1 2
P/N OUT INCOMP
STDT VCC
16 15
0.1
+
3 4
3.3n
5
VCC
LF 6 /2 7V CC 8 SWF
14 CD HSYNC 13 GND 12 OSC 11 DLY 10 FVCAP 9
82n
VCC
100k
STANDARD TRUTH TABLE /2 P/N 0 1 0 1 STANDARD 4:2:2 - 270 4:2:2 - 360 4sc - NTSC 4sc - PAL
0.68
(1)
0 0
VCC
All resistors in ohms, all capacitors in microfarads, all inductors in henries unless otherwise stated.
0.1
180n
1 1
SWF
(1) To reduce board space, the two anti-series 6.8 F capacitors (connected across pins 2 and 3 of the GS9010A) may be replaced with a 1.0 F non-polarized capacitor provided that: (a) the 0.68 F capacitor connected to the OSC pin (11) of the GS9010A is replaced with a 0.33 F capacitor and (b) the GS9005A /15A Loop Filter Capacitor is 10 nF. (2) Remove this potentiometer if P/N function is not required, and ground pin 16 of the GS9010A. (3) The GS9000B will operate to a maximum frequency of 370 Mbps. The GS9000S will operate to a maximum of 300 Mbps.
Fig. 17 Typical Application Circuit
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